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[850] Layout Engineer

Keywords / Skills : I O, Module, CMOS, IP

Posted: 2018-03-13

Manufacturing/ Engineering/ R&D
Design Engineer
Bachelors/ Degree
Posted On
13th Mar 2018
Job Ref code
Job Description
  • Custom layout design, automation and layout optimization to support process characterization/qualification test chip, I/O cell, analog macro and memory layout design
  • Work with R&D and Fab Process Integration & Module teams to help define advanced test chip for new technology development.
  • Provide custom layout design for I/O Cell, Analog Macro and Memory Layout Design
  • New Test Pattern Design & Develop new/sophisticated EDA code for automation test structure generation.
  • Bachelor / Master Degree holders with 5+ years of experience in wafer fabrication or IC Mask design environment.
  • Understand test structures / IP/ macro
  • Knowledge of Semiconductor physics, CMOS device
  • Programming skills

Key Skill(s)

About Company

HPS Partners serve an international client base including early stage organisations and leading global corporations. Our assignments range from senior management appointments to experienced individual contributors.

HPS Partners believe the right people in the right jobs, allow synergies to create a strategy in sync with the dynamic marketplace, economy and competition. The right people are directly related to a seamless operating process that produces results. We help highly qualified senior executives achieve personal growth, job satisfaction and advancements. ​Please tell us a little about your professional experience and aspirations
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