Keyskills: Asic Verification, vhdlVerilog
5-10 year experience in ASIC Design Verification
Expert on SV UVM language, familiar with VHDL/Verilog, perl, C++, knowledge on AHB, Embeded System, Uart, DMA. Know
Posted : 17th Dec 2018
Keyskills: ASIC / SOC tape-out
Summary: ASIC Site lead in Singapore
Posted : November 2018
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Keyskills: SOC, ASIC, Verilog, RTL, System onChip, VLSI Designs, Floor Planning, Clock Tree Synthesis
Summary: Oversees definition, design, verification, and documentation for SoC (System on a Chip) development.
Posted : August 2018
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