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Keywords / Skills : Design For Testability, Verilog, VHDL, Boundary Scan, ATPG

1 - 11 years
Posted: 2019-01-12

IT/Computers - Hardware
Posted On
12th Jan 2019
Job Description
Experience in Design for Test (DFT) of large, lower geometry SOC designs.

• Experience in DFT concepts, test mode.

• Good knowledge in Boundary Scan, ATPG Scan. [Automatic test pattern generation tools]

• Proficiency in VHDL/Verilog coding, testmench setup, test case creation and verification

• Proficiency in mixed signal IP verification such PCIe Phy, PLL etc

• Experience with industry standard tools for DFT and Verification (Synopsys, Cadence)

• Proficiency high level programming and scripting languages such as "C", "C++", Perl

• Knowledge or Experience in Test development and Product engineering will be an added advantage

About Company

Established in 1991, Collabera is one of the fastest growing end-to-end information technology services and solutions companies globally. As a $500 million IT company, Collabera's client-centric business model, commitment to service excellence and Global Delivery Model enables its global 2000 and leading mid-market clients to succeed in an increasingly competitive marketplace.

With over 9000 IT professionals globally, Collabera provides value-added onsite, offsite and offshore technology services and solutions to premier corporations. Over the past few years, Collabera has been awarded numerous accolades and Industry recognitions including.

� Collabera listed in GS 100 - recognized for excellence and maturity
� Collabera named among the Top 500 Diversity Owned Businesses
� Collabera listed in GS 100 & ranked among top 10 service providers
� Collabera was ranked:
� 32 in the Top 100 Large Businesses in the U.S
� 18 in Top 500 Diversity Owned Businesses in the U.S
� 3 in the Top 100 Diversity Owned Businesses in New Jersey
� 3 in the Top 100 Privately-held Businesses in New Jersey
� 66th on FinTech 100
� 35th among top private companies in New Jersey

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