Our client is a semicon MNC involved in integrated circuit design.
Position: Senior Staff / Staff / Senior Physical Design Engineer (several headcount)
• Provide back-end design support to the various business units
• Full-chip PnR; Take charge of chip-level floorplanning, power structure, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna)
• Active participation in working with fronted and integration team.
• Bachelor Degree or above in Electrical Engineering in EDA (Electronic Design Automation), back-end physical design and verification
• 5 – 6 years of physical design experience
• Experience in chip-level PnR
• Familiar with hierarchical physical design strategies, methodologies and deep sub-micron technology issues
• Familiar with back-end physical design flow, mainly floorplanning, congestion analysis, placement optimization, clock-tree synthesis and timing closure
• Proficient in programming/scripting with good coding experience in Tcl/Perl/Python/Tk
• Processes good working ethic, good verbal and written communication skills
• Familiar with tools such as Synopsys IC Compiler/Cadence SoC Encounter and Primetime
• Knowledge on static timing analysis (PrimeTime), EM/IR-Drop/crosstalk analysis (PTSI, Redhawk), formal or physical verification (Calibre) is a plus
Interested applicants please send your updated CV (in Word document format) to firstname.lastname@example.org .