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Timing Closure Jobs

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Responsibilities: Digital IC Design * Perform IC design development of products * Perform Logic Synthesis, Static Timing Analysis * Lead DFT related activities - Scan Insertion, ATPG, Patte

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Position : Electronic Design Engineer (Hardware Design/MCU) Location : Sin Ming Lane (Marymount/Bishan) Working hours : Monday to Friday/ 8 Hours / Office Hours Salary (commensurate with experience

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Physical Design Engineer

Canaan Creative Global Pte. Ltd.
Singapore
2-5 years

Responsibility * Responsible for high performance block implementation (RTL to GDSII). * Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS a

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QUALIFICATION/EXPERIENCE: · Working on RTL design implementation and verification, includes RTL coding, logic synthesis, test bench development, RTL simulation for FPGA prototyping. · Implement digi

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QUALIFICATION/EXPERIENCE: · Working on RTL design implementation and verification, includes RTL coding, logic synthesis, test bench development, RTL simulation for FPGA prototyping. · Implement digi

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QUALIFICATION/EXPERIENCE: · Working on RTL design implementation and verification, includes RTL coding, logic synthesis, test bench development, RTL simulation for FPGA prototyping. · Implement digi

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ROLE AND RESPONSIBILITIES 1. Develop the next generation FPGA & SOC based artificial intelligent software Platform 2. Work closely with suppliers like Xilinx to support the FPGA/Linux software d

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* Develop and implement plans to synthesize, implement including Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ g

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Key responsibilities: Digital IC Design * Perform IC design development of products for FTDI products * Perform Logic Synthesis, Static Timing Analysis * Lead DFT related activities - Scan I

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Responsibilities * Working on 16nm and below advanced process project APR and sign-off. * Take the TOP and PM role for the complicated hierarchical chip (more than 20m plus 500+ macros). * Ta

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Senior Digital IC Design Engineer

Jl Semi Singapore Pte. Ltd.
Singapore
10-15 years

JL Semi is pushing the boundary of automotive and industry Ethernet technology. Innovations in silicon architecture & design coupled with advance process nodes, our products deliver industry leading p

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JOB DESCRIPTION · Work with SoC Integration and SoC Timing on power structure optimization · Work on UPF development to support different stages of implementation flow and SoC verification · Work o

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JOB DESCRIPTION · Work with system engineers on timing requirements and feedback on optimization. · Work on SoC timing constraint, synthesis and timing closure. · Work on power structure, eg. Isola

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Job Description: 1. Responsible for the entire process from RTL to GDS; 2. Responsible for block level timing closure, formal check, low power check and power analysis; 3. Responsible for block le

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Job Description: 1. Responsible for the entire process from RTL to GDS; 2. Responsible for block level timing closure, formal check, low power check and power analysis; 3. Responsible for block le

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Job Description: · Develop Verilog RTL code based on design specification · Write test-bench for RTL verification in Verilog and System Verilog · Design validation in FPGA and Silicon · Develop co

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Physical Design Engineer

Realtek Singapore Private Limited
Singapore
0-1 years

JOB DESCRIPTION To provide back-end design support to the various business units, taking care of System-on-Chip top-level floorplanning, partitioning and timing budgeting, power structure, place and

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Technical Trainer Manager

Excelpoint Systems (pte) Ltd
Singapore
7-10 years

Roles & Responsibilities We are seeking to hire an TTM for Embedded System, who is proficient in delivering training content relevant to the field of Embedded Systems applications, like FPGA, IoT/AI

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QUALIFICATION/EXPERIENCE: · Working on RTL design implementation and verification, includes RTL coding, logic synthesis, test bench development, RTL simulation for FPGA prototyping. · Implement digi

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QUALIFICATION/EXPERIENCE: · Working on RTL design implementation and verification, includes RTL coding, logic synthesis, test bench development, RTL simulation for FPGA prototyping. · Implement digi

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QUALIFICATION/EXPERIENCE: · Working on RTL design implementation and verification, includes RTL coding, logic synthesis, test bench development, RTL simulation for FPGA prototyping. · Implement digi

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Job Description * Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing. * Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation e

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Physical Design Engineer

Adecco Personnel Pte Ltd
Singapore
2-5 years

Job Description * Fully responsible for Netlist-to-GDS physical design implementation of low power chips * Responsible for physical design, development for variety of SoC(System On Chip) and tap

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Service Manager, IT Security Services 1702

Aspire Nxt Pte. Ltd.
Singapore
10-15 years

Job Responsibilities The Team Manager has a wide spectrum of responsibilities and actions. As the manager of his/her team, he/she: * assigns the tasks and manages delegation, * sets and review

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Project Administrator

Emerson Asia Pacific Private Limited
Singapore
5-7 years

Description: Position is responsible for supporting project administration and documentation for Flow Controls in AP region. Job Responsibilities: Project Administration: * Assists Project Ma

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