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Senior Design Verification Engineer

Uni Connect Pte Ltd
Singapore
2-5 years

. Bachelor/Master Degree in EEE/Computer/IC design . 2-10 years verification experiences . IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU . Experience and debuggin

Skills :

Design Verification Engineer

Uni Connect Pte Ltd
Singapore
2-5 years

. Bachelor/Master Degree in EEE/Computer/IC design . 2-4 years verification experiences . IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU . Experience and debugging

Skills :

Senior Layout Engineer

Uni Connect Pte Ltd
Singapore
2-5 years

Responsibilities: * To contribute to the development of High-Speed Connectivity, Broadband Analog and Computing/Storage-Memory Data-Transport products (including functional blocks such as high-spee

Skills :

Senior Physical Design engineer

Uni Connect Pte Ltd
Singapore
5-7 years

Responsible for physical design, development of variety of SoC (System On Chip) and tapeout. - Execute state-of-art methodologies include synthesis, floor-planning, place and route, RC extraction,

Skills :

Layout Engineer

Uni Connect Pte Ltd
Singapore
2-5 years

Responsibilities: * To contribute to the development of High-Speed Connectivity, Broadband Analog and Computing/Storage-Memory Data-Transport products (including functional blocks such as high-spee

Skills :

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